As LSI circuits and 3D memories have been becoming smaller in size with more layers, increases in interconnect delay in metal interconnects have become a serious problem. To reduce interconnect delay, it is essential to reduce the interconnect resistance and the capacitance between interconnects. To lower the resistance of interconnects, a low-resistance material such as Cu has been used in practice. With Cu interconnects, however, there are problems such as reliability degradation due to stress migration or electromigration, and increases in electrical resistivity due to size effects. Therefore, there is an increasing demand for interconnect materials with a low resistance and a high current density tolerance.
As the next-generation interconnect materials to achieve a lower resistance and higher reliability, attention is being paid to application of carbon-based materials such as carbon nanotubes or graphene having excellent physical properties such as a high current density tolerance, high electrical conductivity, and high heat conductivity. Particularly, structures having carbon nanotubes arranged as vertical interlayer interconnects and graphene as horizontal interconnects have been studied.
In a case where a graphene layer as a horizontal interconnect has a multilayer structure, however, only the uppermost layer in the multilayer graphene layer is in contact with the carbon nanotube catalyst/a foundation layer at the bottom portion of a contact hole. The resistance between graphene layers is a hundred or more times higher than the graphene bulk resistance. Therefore, there is a possibility that only the conduction through the uppermost layer can be used.